The present invention relates to a phase locked loop circuit having a frequency modulation function and a method of frequency modulation in phase locked loop circuit.
A phase locked loop circuit has widely been used for generating a clock signal for operations of digital devices in synchronizing with a stable reference frequency input.
The frequency of the clock signal generated from the phase locked loop circuit is normally constant- The phase locked loop circuit generates the clock signal of the constant frequency, whereby an electro-magnetic interference is also caused. Such the electro-magnetic interference may be reduced by a frequency modulation to the frequency of the clock generator. A triangle waveform modulation is effective, wherein a linear variation in frequency is periodically made.
FIG. 1 is a block diagram illustrative of a first conventional phase locked loop circuit having a first conventional frequency modulation function FIG. 2 is a diagram illustrative of a frequency variation of an output clock signal over time of the first conventional phase locked loop circuit of FIG. 1. The first conventional phase locked loop circuit comprises a phase comparator (PFD) 101, a charge pump circuit (CP) 102, a low pass filer (LPF) 103, a voltage control oscillator (VCO) 104, a loop counter 105, a read only memory table 106, and an up-down counter 107.
The voltage control oscillator (VCO) 104 outputs a clock signal which varies in frequency “fo” in response to a controlled voltage from the low pass filter 103. The loop counter 105 counts pulses of the clock signal, and when a counted value reaches a given value corresponding to a frequency dividing rate given by the ROM table 106, then the frequency-dividing pulse of a frequency “fb” is outputted. The phase comparator 101 compares, in frequency, the input of the reference frequency “fr” to the frequency-divided pulse. The charge pump circuit 102 generates a positive or negative current in accordance with the direct current output from the phase comparator 101 for charging or discharging a non-illustrative capacitor of the low pass filter 103. The low pass filter 103 generates the control voltage having a voltage level corresponding to a difference between the reference frequency “fr” and the frequency “fb” of the frequency-dividing pulse, so that the control voltage is supplied to the voltage control oscillator 104. Under such the loop feedback control, the oscillation frequency is controlled by the voltage control oscillator 104, so that the frequency of the output clock signal follows the reference frequency at a predetermined relationship.
The up-down counter 107 up-counts or down-counts the frequency-dividing pulse from the loop counter 105. The ROM table 106 reads out the values of the frequency-dividing rates previously stored in accordance with the address corresponding to the counted value by the up-down counter 107 so as to supply the read out values to the loop counter 105.
The frequency-dividing rate is sequentially increased upon the up-count whereby the output clock frequency “fo” is risen. The frequency-dividing rate is sequentially decreased upon the down-count whereby the output clock frequency “fo” is fallen. The frequency-dividing values are stored in the ROM in the order of the addresses of the ROM table 106 so that the up-count and the down-count are alternatively made in the order of the address of the ROM table 106. The frequency of the output clock signal is alternatively risen and fallen. As a result, the frequency-modulated lock signal is thus generated. In this case, a relationship between the frequency-dividing values and the address stored in the ROM table 106 is adjusted to generate the frequency-modulated clock signal in the triangle waveform as shown in FIG. 2.
The first conventional phase locked loop circuit having the conventional frequency modulation function includes the ROM, for which reason the necessary chip size for accommodating the circuit is large. It is, therefore, required to provide a phase locked loop circuit capable of generating a frequency-modulated clock signal, wherein the predetermined control values are externally inputted for programmable operations without using the ROM.
FIG. 3 is a block diagram illustrative of a second conventional phase locked loop circuit having a second conventional frequency modulation function. FIG. 4 is a view illustrative of a control to frequency-dividing rate of loop counter in the second conventional phase locked loop circuit of FIG. 3. FIG. 5 is a diagram illustrative of variation in frequency of the clock signal over time when the frequency-dividing rate is changed in the second conventional phase locked loop circuit of FIG. 3. This second conventional phase locked loop circuit is disclosed in Japanese laid-open paten publication No. 11-9876. The second conventional phase locked loop circuit comprises a phase comparator (PFD) 201, a charge pump circuit (CP) 202, a low pass filer (LPF) 203, a voltage control oscillator (VCO) 204, a loop counter 205, an arithmetic circuit 206, a control signal generator circuit 207, and a multiplexer 208.
The loop counter 205 counts pulses of the clock signal, and when a counted value reaches a given value corresponding to a frequency dividing rate N0 or N1 given by the multiplexer 208, then the frequency-dividing pulse Nout is outputted. The phase comparator 201 compares, in frequency, the input of the reference frequency “fr” to the frequency-divided pulse. The charge pump circuit 202 generates a positive or negative current in accordance with the direct current output from the phase comparator 201 for charging or discharging a non-illustrative capacitor of the low pass filter 203. The low pass filter 203 generates the control voltage having a voltage level corresponding to a difference between the reference frequency “fr” and the frequency “fb” of the frequency-dividing pulse, so that the control voltage is supplied to the voltage control oscillator 204. Under such the loop feedback control, the oscillation frequency is controlled by the voltage control oscillator 204, so that the frequency of the output clock signal follows the reference frequency at a predetermined relationship.
The arithmetic circuit 206 operates the integer number “V” based on the externally given signals “M” and “D” and outputs the integer number “V”. The control signal generator circuit 207 generates a control signal “PS” for controlling the switching operation of the multiplexer 208 with reference to the reference frequency “fr” based on the signal “M” and the integer number “V”. The multiplexer 208 switches the frequency dividing rates N0 and N1 in accordance with the control signal “PS” in order to output the switched frequency dividing rate to the loop counter 205. The signal “M” is such a signal that the number of the frequency-divided pulses in one modulation time period of the clock signal generated from the phase locked loop circuit is “aM”, wherein “a” is the positive even number, for example, 4. The signal “D” is a modulation scaling signal which decides a difference of the maximum frequency and the minimum frequency of the frequency-modulated clock signal.
The conventional method of controlling the frequency-dividing rate of the loop counter will be described with reference to FIG. 4. There are two frequency-dividing rates N0 and N1 to be given to the loop counter 205, for example, N0<N1. The frequency-dividing rate N0 corresponds to “0” of the control signal PS. The frequency-dividing rate N1 corresponds to “1” of the control signal PS. One of the two frequency-dividing rates N0 and N1 is given to the loop counter 205. If the integer number “V” is 0, then in the first time period T1, the control signal “PS” remains 0, and then the control signal “PS” is changed from 0 to 1 at a boundary between the first and second time periods T1 and T2 before in the second time period T2, the control signal “PS” remains 1. After the second time period T2, the control signal “PS” is changed from 1 to 0. The clock frequency “fo” shows step-like change at the starting and terminating points of the first time period T1 and the starting and terminating points of the second time period T2. If the integer number “V” is increased, then the changes between “0” and “1”, appear at each point of the starting and terminating points of the first and second time periods T1 and T2, even in the remaining periods except for the starting and terminating points, the control signal “PS” remains “1” or “0”.
If the frequency-dividing rate is changed, the frequency of the clock signal generated by the phase locked loop circuit is changed to follow to a transition property which mainly depends on the characteristics of the charge pump circuit 202 and the low pass filter 203 and the gain of the voltage control oscillator 204.
For example, as shown in FIG. 5, if at a time “t1”, the control signal “PS” is changed from “0” to “1”, then the clock signal frequency is changed from a value corresponding to the frequency-dividing rate N0 through a transitional variation to a different value corresponding to the frequency-dividing rate N1 before the control signal “PS” becomes stable in accordance with the lock of the phase locked loop operation.
The variation in the frequency of the clock signal upon change o the frequency-dividing rate appears with a transitional delay. If the frequency dividing rate is changed before the phase of the clock signal changed upon the previous change of the previous is locked at the phase of the reference frequency signal, then the variation in the frequency of the clock signal is smoothed. This smoothing is remarkable as the integer number “V” is large.
The arithmetic circuit 206 generates an optimum integer number “V” in accordance with the values “M” and “D”, wherein the value “M” represents the number of the frequency-divided pulse Nout corresponding to one-modulation time period of the clock signal frequency, whilst the value “D” represents the modulation scaling signal which decides the difference between the maximum and minimum values of the clock frequency. The second conventional phase locked loop circuit shown in FIG. 3 is capable of generating the frequency-modulated clock signal, wherein the clock frequency varies in the form of the triangle waveform.
The above Japanese laid-open patent publication does not disclose the circuit configuration of the control circuit necessary for generating the control signal “PS”.
In the above circumstances, it had been required to develop a novel a phase locked loop circuit having a frequency modulation function and a method of frequency modulation in phase locked loop circuit free from the above problem.